现代VLSI设计 基于IP核的设计 英文版2025|PDF|Epub|mobi|kindle电子书版本百度云盘下载

现代VLSI设计 基于IP核的设计 英文版PDF格式电子书版下载

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Chapter 1 Digital Systems and VLSI1

1.1 Why Design Integrated Circuits?3

1.2 Integrated Circuit Manufacturing5

1.2.1 Technology5

1.2.2 Economics8

1.3 CMOS Technology18

1.3.1 Power Consumption18

1.3.2 Design and Testability19

1.3.3 Reliability20

1.4 Integrated Circuit Design Techniques21

1.4.1 Hierarchical Design22

1.4.2 Design Abstraction25

1.4.3 Computer-Aided Design31

1.5 IP-Based Design33

1.5.1 Why IP?33

1.5.2 Types of IP34

1.5.3 IP Across the Design Hierarchy35

1.5.4 The IP Life Cycle37

1.5.5 Creating IP37

1.5.6 Using IP39

1.6 A Look into the Future40

1.7 Summary41

1.8 References42

1.9 Problems42

Chapter 2 Fabrication and Devices43

2.1 Introduction45

2.2 Fabrication Processes45

2.2.1 Overview46

2.2.2 Fabrication Steps48

2.3 Transistors52

2.3.1 Structure of the Transistor52

2.3.2 A Simple Transistor Model57

2.3.3 Transistor Parasitics60

2.3.4 Tub Ties and Latchup61

2.3.5 Advanced Transistor Characteristics64

2.3.6 Leakage and Subthreshold Currents70

2.3.7 Thermal Effects72

2.3.8 Spice Models72

2.4 Wires and Vias73

2.4.1 Wire Parasitics76

2.4.2 Skin Effect in Copper Interconnect82

2.5 Fabrication Theory and Practice84

2.5.1 Fabrication Errors85

2.5.2 Scaling Theory and Practice87

2.5.3 SCMOS Design Rules90

2.5.4 Typical Process Parameters95

2.5.5 Lithography for Nanometer Processes95

2.5.6 3-D Integration97

2.6 Reliability98

2.6.1 Traditional Sources of Unreliability99

2.6.2 Reliability in Nanometer Technologies101

2.7 Layout Design and Tools103

2.7.1 Layouts for Circuits103

2.7.2 Stick Diagrams106

2.7.3 Hierarchical Stick Diagrams108

2.7.4 Layout Design and Analysis Tools113

2.7.5 Automatic Layout117

2.8 References119

2.9 Problems120

Chapter 3 Logic Gates123

3.1 Introduction125

3.2 Combinational Logic Functions125

3.3 Static Complementary Gates128

3.3.1 Gate Structures128

3.3.2 Basic Gate Layouts133

3.3.3 Logic Levels137

3.3.4 Delay and Transition Time140

3.3.5 Power Consumption148

3.3.6 The Speed-Power Product152

3.3.7 Layout and Parasitics152

3.3.8 Driving Large Loads156

3.4 Switch Logic157

3.5 Alternative Gate Circuits159

3.5.1 Pseudo-nMOS Logic159

3.5.2 DCVS Logic162

3.5.3 Domino Logic163

3.6 Low-Power Gates169

3.7 Delay through Resistive Interconnect175

3.7.1 Delay through an RC Transmission Line175

3.7.2 Delay through RC Trees179

3.7.3 Buffer Insertion in RC Transmission Lines182

3.7.4 Crosstalk between RC Wires184

3.8 Delay through Inductive Interconnect187

3.8.1 RLC Basics187

3.8.2 RLC Transmission Line Delay188

3.8.3 Buffer Insertion in RLC Transmission Lines191

3.9 Design-for-Yield193

3.10 Gates as IP195

3.11 References198

3.12 Problems199

Chapter 4 Combinational Logic Networks205

4.1 Introduction207

4.2 Standard Cell-Based Layout207

4.2.1 Single-Row Layout Design208

4.2.2 Standard Cell Layout Design217

4.3 Combinational Network Delay219

4.3.1 Fanout220

4.3.2 Path Delay222

4.3.3 Transistor Sizing226

4.3.4 Logic Synthesis234

4.4 Logic and Interconnect Design235

4.4.1 Delay Modeling236

4.4.2 Wire Sizing238

4.4.3 Buffer Insertion238

4.4.4 Crosstalk Minimization240

4.5 Power Optimization246

4.5.1 Power Analysis247

4.6 Switch Logic Networks251

4.7 Combinational Logic Testing255

4.7.1 Gate Testing256

4.7.2 Combinational Network Testing259

4.7.3 Testing and Yield261

4.8 References262

4.9 Problems262

Chapter 5 Sequential Machines267

5.1 Introduction269

5.2 Latches and Flip-Flops269

5.2.1 Timing Diagrams269

5.2.2 Categories of Memory Elements270

5.2.3 Latches272

5.2.4 Flip-Flops279

5.3 Sequential Systems and Clocking Disciplines281

5.3.1 Clocking Disciplines282

5.3.2 One-Phase Systems for Flip-Flops283

5.3.3 Two-Phase Systems for Latches284

5.4 Performance Analysis292

5.4.1 Performance of Flip-Flop-Based Systems293

5.4.2 Performance of Latch-Based Systems297

5.4.3 Clock Skew299

5.4.4 Retiming308

5.4.5 Transient Errors and Reliability309

5.5 Clock Generation310

5.6 Sequential System Design312

5.6.1 Structural Specification of Sequential Machines312

5.6.2 State Transition Graphs and Tables314

5.6.3 State Assignment323

5.7 Power Optimization329

5.8 Design Validation330

5.9 Sequential Testing332

5.10 References340

5.11 Problems340

Chapter 6 Subsystem Design345

6.1 Introduction347

6.2 Combinational Shifters349

6.3 Adders352

6.4 ALUs360

6.5 Multipliers360

6.6 High-Density Memory369

6.6.1 ROM372

6.6.2 Static RAM372

6.6.3 The Three-Transistor Dynamic RAM376

6.6.4 The One-Transistor Dynamic RAM378

6.6.5 Flash Memory380

6.7 Image Sensors382

6.8 Field-Programmable Gate Arrays385

6.9 Programmable Logic Arrays387

6.10 Buses and Networks-on-Chips391

6.10.1 Bus Circuits391

6.10.2 Buses as Protocols392

6.10.3 Protocols and Specifications394

6.10.4 Logic Design for Buses398

6.10.5 Microprocessor and System Buses405

6.10.6 Networks-on-Chips410

6.11 Data Paths415

6.12 Subsystems as IP417

6.13 References422

6.14 Problems422

Chapter 7 Floorplanning425

7.1 Introduction427

7.2 Floorplanning Methods427

7.2.1 Chip-Level Physical Design427

7.2.2 Block Placement and Channel Definition431

7.2.3 Global Routing436

7.2.4 Switchbox Routing437

7.3 Global Interconnect439

7.3.1 Interconnect Properties and Wiring Plans439

7.3.2 Power Distribution440

7.3.3 Clock Distribution445

7.4 Floorplan Design450

7.4.1 Floorplanning Tips450

7.4.2 Design Validation451

7.5 Off-Chip Connections452

7.5.1 Packages452

7.5.2 The I/O Architecture457

7.5.3 Pad Design458

7.6 References461

7.7 Problems462

Chapter 8 Architecture Design471

8.1 Introduction473

8.2 Hardware Description Languages473

8.2.1 Modeling with Hardware Description Languages474

8.2.2 VHDL479

8.2.3 Verilog487

8.2.4 C as a Hardware Description Language494

8.3 Register-Transfer Design495

8.3.1 Data Path-Controller Architectures497

8.3.2 ASM Chart Design500

8.4 Pipelining509

8.5 High-Level Synthesis518

8.5.1 Functional Modeling Programs519

8.5.2 Data520

8.5.3 Control530

8.5.4 Data and Control535

8.5.5 Design Methodology538

8.6 Architectures for Low Power539

8.6.1 Gate Power Control540

8.6.2 Data Latching541

8.6.3 Clock Gating541

8.6.4 Architecture-Driven Voltage Scaling541

8.6.5 Dynamic Voltage and Frequency Scaling543

8.7 GALS Systems544

8.8 Architecture Testing545

8.9 IP Components550

8.10 Design Methodologies551

8.11 Multiprocessor System-on-Chip Design559

8.12 References565

8.13 Problems565

Appendix A A Chip Designer's Lexicon571

Appendix B Hardware Description Languages589

B.1 Introduction589

B.2 Verilog589

B.2.1 Syntactic Elements589

B.2.2 Data Types and Declarations590

B.2.3 Operators590

B.2.4 Statements591

B.2.5 Modules and Program Units592

B.2.6 Simulation Control593

B.3 VHDL594

B.3.1 Syntactic Elements594

B.3.2 Data Types and Declarations594

B.3.3 Operators595

B.3.4 Sequential Statements595

B.3.5 Structural Statements597

B.3.6 Design Units597

B.3.7 Processes598

References599

Index613