模拟CMOS集成电路设计 影印版2025|PDF|Epub|mobi|kindle电子书版本百度云盘下载

模拟CMOS集成电路设计 影印版PDF格式电子书版下载

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1 Introduction to Analog Design1

1.1 Why Analog？1

1.2 Why Integrated？6

1.3 Why CMOS？6

1.4 Why This Book？7

1.5 General Concepts7

1.5.1 Levels of Abstraction7

1.5.2 Robust Analog Design7

2 Basic MOS Device Physics9

2.1 General Considerations10

2.1.1 MOSFET as a Switch10

2.1.2 MOSFET Structure10

2.1.3 MOS Symbols12

2.2 MOS I/V Characteristics13

2.2.1 Threshold Voltage13

2.2.2 Derivation of I/V Characteristics15

2.3 Second-Order Effects23

2.4 MOS Device Models28

2.4.1 MOS Device Layout28

2.4.2 MOS Device Capacitances29

2.4.3 MOS Small-Signal Model33

2.4.4 MOS SPICE models36

2.4.5 NMOS versus PMOS Devices37

2.4.6 Long-Channel versus Short-Channel Devices38

3 Single-Stage Amplifiers47

3.1 Basic Concepts47

3.2 Common-Source Stage48

3.2.1 Common-Source Stage with Resistive Load48

3.2.2 CS Stage with Diode-Connected Load53

3.2.3 CS Stage with Current-Source Load58

3.2.4 CS Stage with Triode Load59

3.2.5 CS Stage with Source Degeneration60

3.3 Source Follower67

3.4 Common-Gate Stage76

3.5 Cascode Stage83

3.5.1 Folded Cascode90

3.6 Choice of Device Models92

4 Differential Amplifiers100

4.1 Single-Ended and Differential Operation100

4.2 Basic Differential Pair103

4.2.1 Qualitative Analysis104

4.2.2 Quantitative Analysis107

4.3 Common-Mode Response118

4.4 Differential Pair with MOS Loads124

4.5 Gilbert Cell126

5 Passive and Active Current Mirrors135

5.1 Basic Current Mirrors135

5.2 Cascode Current Mirrors139

5.3 Active Current Mirrors145

5.3.1 Large-Signal Analysis149

5.3.2 Small-Signal Analysis151

5.3.3 Common-Mode Properties154

6 Frequency Response of Amplifiers166

6.1 General Considerations166

6.1.1 Miller Effect166

6.1.2 Association of Poles with Nodes169

6.2 Common-Source Stage172

6.3 Source Followers178

6.4 Common-Gate Stage183

6.5 Cascode Stage185

6.6 Differential Pair187

Appendix A：Dual of Miller’s Theorem193

7 Noise201

7.1 Statistical Characteristics of Noise201

7.1.1 Noise Spectrum203

7.1.2 Amplitude Distribution206

7.1.3 Correlated and Uncorrelated Sources207

7.2 Types of Noise209

7.2.1 Thermal Noise209

7.2.2 Flicker Noise215

7.3 Representation of Noise in Circuits218

7.4 Noise in Single-Stage Amplifiers224

7.4.1 Common-Source Stage225

7.4.2 Common-Gate Stage228

7.4.3 Source Followers231

7.4.4 Cascode Stage232

7.5 Noise in Differential Pairs233

7.6 Noise Bandwidth239

8 Feedback246

8.1 General Considerations246

8.1.1 Properties of Feedback Circuits247

8.1.2 Types of Amplifiers254

8.2 Feedback Topologies258

8.2.1 Voltage-Voltage Feedback258

8.2.2 Current-Voltage Feedback263

8.2.3 Voltage-Current Feedback266

8.2.4 Current-Current Feedback269

8.3 Effect of Loading270

8.3.1 Two-Port Network Models270

8.3.2 Loading in Voltage-Voltage Feedback272

8.3.3 Loading in Current-Voltage Feedback275

8.3.4 Loading in Voltage-Current Feedback278

8.3.5 Loading in Current-Current Feedback281

8.3.6 Summary of Loading Effects283

8.4 Effect of Feedback on Noise284

9 Operational Amplifiers291

9.1 General Considerations291

9.1.1 Performance Parameters291

9.2 One-Stage Op Amps296

9.3 Two-Stage Op Amps307

9.4 Gain Boosting309

9.5 Comparison313

9.6 Common-Mode Feedback314

9.7 Input Range Limitations325

9.8 Slew Rate326

9.9 Power Supply Rejection334

9.10 Noise in Op Amps336

10 Stability and Frequency Compensation345

10.1 General Considerations345

10.2 Multipole Systems349

10.3 Phase Margin351

10.4 Frequency Compensation355

10.5 Compensation of Two-Stage Op Amps361

10.5.1 Slewing in Two-Stage Op Amps368

10.6 Other Compensation Techniques369

11 Bandgap References377

11.1 General Considerations377

11.2 Supply-Independent Biasing377

11.3 Temperature-Independent References381

11.3.1 Negative-TC Voltage381

11.3.2 Positive-TC Voltage382

11.3.3 Bandgap Reference384

11.4 PTAT Current Generation390

11.5 Constant-Gm Biasing392

11.6 Speed and Noise Issues393

11.7 Case Study397

12 Introduction to Switched-Capacitor Circuits405

12.1 General Considerations405

12.2 Sampling Switches410

12.2.1 MOSFETS as Switches410

12.2.2 Speed Considerations414

12.2.3 Precision Considerations417

12.2.4 Charge Injection Cancellation421

12.3 Switched-Capacitor Amplifiers423

12.3.1 Unity-Gain Sampler/Buffer424

12.3.2 Noninverting Amplifier432

12.3.3 Precision Multiply-by-Two Circuit438

12.4 Switched-Capacitor Integrator439

12.5 Switched-Capacitor Common-Mode Feedback442

13 Nonlinearity and Mismatch448

13.1 Nonlinearity448

13.1.1 General Considerations448

13.1.2 Nonlinearity of Differential Circuits452

13.1.3 Effect of Negative Feedback on Nonlinearity454

13.1.4 Capacitor Nonlinearity457

13.1.5 Linearization Techniques458

13.2 Mismatch463

13.2.1 Offset Cancellation Techniques471

13.2.2 Reduction of Noise by Offset Cancellation476

13.2.3 Alternative Definition of CMRR478

14 Oscillators482

14.1 General Considerations482

14.2 Ring Oscillators484

14.3 LC Oscillators495

14.3.1 Crossed-Coupled Oscillator499

14.3.2 Colpitts Oscillator502

14.3.3 One-Port Oscillators505

14.4 Voltage-Controlled Oscillators510

14.4.1 Tuning in Ring Oscillators512

14.4.2 Tuning in LC Oscillators521

14.5 Mathematical Model of VCOs525

15 Phase-Locked Loops532

15.1 Simple PLL532

15.1.1 Phase Detector532

15.1.2 Basic PLL Topology533

15.1.3 Dynamics of Simple PLL542

15.2 Charge-Pump PLLs549

15.2.1 Problem of Lock Acquisition549

15.2.2 Phase/Frequency Detector and Charge Pump550

15.2.3 Basic Charge-Pump PLL556

15.3 Nonideal Effects in PLLs562

15.3.1 PFD/CP Nonidealities562

15.3.2 Jitter in PLLs567

15.4 Delay-Locked Loops569

15.5 Applications572

15.5.1 Frequency Multiplication and Synthesis572

15.5.2 Skew Reduction574

15.5.3 Jitter Reduction576

Appendix A Short-Channel Effects and Device Models579

A.1 Scaling Theory579

A.2 Short-Channel Effects583

A.2.1 Threshold Voltage Variation583

A.2.2 Mobility Degradation with Vertical Field585

A.2.3 Velocity Saturation587

A.2.4 Hot Carrier Effects589

A.2.5 Output Impedance Variation with Drain-Source Voltage589

A.3 MOS Device Models591

A.3.1 Level 1 Model592

A.3.2 Level 2 Model593

A.3.3 Level 3 Model595

A.3.4 BSM Series596

A.3.5 Other Models597

A.3.6 Charge and Capacitance Modeling598

A.3.7 Temperature Dependence599

A.4 Process Corners599

A.5 Analog Design in a Digital World600

Appendix B CMOS Processing Technology604

B.1 General Considerations604

B.2 Wafer Processing605

B.3 Photolithography606

B.4 Oxidation608

B.5 Ion Implantation608

B.6 Deposition and Etching611

B.7 Device Fabrication611

B.7.1 Active Devices611

B.7.2 Passive Devices616

B.7.3 Interconnects624

B.8 Latch-Up627

Appendix C Layout and Packaging631

C.1 General Layout Considerations631

C.1.1 Design Rules632

C.1.2 Antenna Effect634

C.2 Analog Layout Techniques635

C.2.1 Multifinger Transistors635

C.2.2 Symmetry637

C.2.3 Reference Distribution642

C.2.4 Passive Devices644

C.2.5 Interconnects653

C.3 Substrate Coupling660

Index677