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Chapter 1 Phases of an ASIC Project1

1.1 Introduction1

1.2 List of Phases1

1.3 Prestudy Phase3

1.4 Top-Level Design Phase5

1.5 Module Specification Phase8

1.5.1 Tasks for the Bulk of the Team9

1.5.2 Other Tasks10

1.6 Module Design11

1.6.1 Tasks for the Bulk of the Team12

1.6.2 Other Tasks13

Preface15

CONTENTS15

1.7 Subsystem Simulation15

1.7.1 Tasks for the Subsystem Simulation Team16

1.7.2 Project Leader Tasks17

1.8 System Simulation/Synthesis17

1.8.1 Tasks for the System Simulation Team18

Acknowledgments19

1.8.2 Tasks for the Synthesis Team21

1.8.3 Project Leader Tasks22

1.9 Layout and the Backend Phase23

1.10 Postlayout Simulation/Synthesis25

1.11 ASIC Sign-Off27

1.12 Preparation for Testing Silicon28

1.13 Testing of Silicon30

1.13.1 Project Leader Tasks32

1.14 Summary33

Chapter 2 Design Reuse and System-on-a-Chip Designs35

2.1 Introduction35

2.2 Reuse Documentation36

2.2.1 Functional Overview36

2.2.2 Interface Description36

2.2.3 Implementation Details37

2.2.4 Timing Diagrams37

2.2.5 Test Methodology37

2.2.6 Clocking Strategy37

2.2.10 Programmer's Reference Guide38

2.2.9 Module Validation Approach38

2.2.7 Source Code Control Strategy38

2.2.8 Synthesis/Layout Approach38

2.3 Tips and Guidelines for Reuse39

2.3.1 Company Standards39

2.3.2 Coding Style39

2.3.3 Generics and Constants40

2.3.4 Clock Domains,Synchronous Design,Registers and Latches41

2.3.5 Use of Standard Internal Buses42

2.3.6 CPU-Addressable Registers42

2.3.8 Verification,Testbenches and Debugging43

2.3.7 Technology Specifics43

2.3.9 VHDL versus Verilog44

2.3.10 Live Documentation44

2.3.11 Reviewing44

2.4 SoC and Third-Party IP Integration44

2.4.1 Developing In-House versus Sourcing Externally45

2.4.2 Where to Source IP46

2.4.3 Reducing the Risk with Parallel Third-Party IP Development47

2.4.4 Issues with Third-Party IP48

2.4.5 Processor and DSP Cores50

2.5 System-Level Design Languages51

2.6 Virtual Socket Interface Alliance51

2.7 Summary51

Chapter 3 A Quality Design Approach53

3.1 Introduction53

3.2.1 Specifications54

3.2.2 Hierarchy Diagram54

3.2 Project Design Documentation54

3.2.3 Design Route Document55

3.2.4 Module Documentation56

3.2.5 The Test Approach Document56

3.3 Reviews57

3.3.1 Review of the Architecture Specification/Register Specifications58

3.4 Module Design and Reviewing58

3.4.1 Module Specification58

3.4.2 Module Design Phase60

3.4.3 Module Coding Phase62

3.4.4 Module Simulation/Synthesis Phase63

3.6 Review Checklists64

3.6.1 Specification Review Checklist64

3.5 Quality System Simulations64

3.6.2 Design Documentation Review Checklist65

3.6.3 Coding Phase Review Checklist65

3.7 Summary66

4.1 Introduction69

4.2 General Coding Guidelines69

Chapter 4 Tips and Guidelines69

4.2.1 Simplicity70

4.2.2 User-Defined Types and Complex Data Types70

4.2.3 Naming Conventions71

4.2.4 Constants72

4.2.5 Use of Comments72

4.2.6 Indentation73

4.2.7 Ordering I/O Signals and Variable Declarations74

4.2.8 Consistent Logic Assertion Levels74

4.2.9 Use of Hierarchy and Design Partitioning75

4.2.10 Unused States in State Machines76

4.2.12 Modular Interfaces77

4.2.11 Glitch Sensitivity77

4.3 Coding for Synthesis78

4.3.1 Inferred Latches78

4.3.2 Sensitivity Lists79

4.3.3 Registering Module Outputs79

4.3.4 Reset Values on Registered Signals80

4.3.5 State Machine Coding Styles80

4.3.7 Resource Sharing81

4.3.6 Multiplexers and Priority81

4.3.8 Constructs That Will Not Synthesize83

4.4 Coding for Testability83

4.4.1 Coding for Functional Simulation/Functional Verification83

4.4.2 Scan-Test Issues86

4.5 Coding for Multiple Clock Domains87

4.5.1 Use of Multiple Clocks87

4.5.2 Crossing Clock Boundaries88

4.6 Summary92

5.1 Introduction93

Chapter 5 ASIC Simulation and Testbenches93

5.2 Quality Testbenches94

5.2.1 Generating Input Stimuli95

5.2.2 Running the Tests97

5.2.3 Comparing and Logging the Results99

5.3 Simulation Strategy101

5.3.1 Software Hierarchy102

5.3.2 The Software Driver Testbench102

5.3.3 C Model Cosimulation103

5.3.4 Co-Verification Tool104

5.3.5 Converting the C Code105

5.4 Extending the Simulation Strategy105

5.5 Reducing Top-Level Simulation Run Times106

5.5.1 Increasing Workstation Performance106

5.5.2 Changing Simulation Tools107

5.5.3 Analysis of Simulation Statement Executions107

5.5.4 Preloading RAMs107

5.5.5 Using Behavioral Models/Test Modes107

5.6.2 Source Code Debugging108

5.6.1 Saving Simulation Snapshots108

5.6 Speeding Up Debugging108

5.5.6 Running Tests in Batch Mode108

5.7 Different Types of Testing109

5.7.1 Module Testing109

5.7.2 Subsystem Testing110

5.7.3 Chip-Level Testing111

5.7.4 Gate-Level Testing111

5.7.6 Board-Level Testing112

5.8 Generation of ASIC Test Vectors112

5.7.5 Postlayout Testing112

5.9 Summary113

Chapter 6 Synthesis115

6.1 Introduction115

6.2 The General Principle116

6.3 Top-Down versus Bottom-Up Synthesis116

6.4 Physical Synthesis Tools117

6.5 Scripts versus GUIs118

6.6 Common Steps in Synthesis Scripts119

6.6.1 Sample Script Action Sequence119

6.6.2 Sample Scripts123

6.7 Directory Structures129

6.8 Special Cells129

6.8.1 Handling Memory Cells129

6.8.2 I/O Cells130

6.8.3 Other Special Cells130

6.9 Miscellaneous Synthesis Terms,Concepts and Issues130

6.9.1 Timing Paths131

6.9.3 Timing Margins/Time Budgeting132

6.9.2 Latches versus Flip-Flops132

6.9.4 Characterize and Compile133

6.9.5 Overconstraining Designs133

6.9.6 Grouping and Weighting134

6.9.7 Flattening134

6.9.8 dont_touch Attributes135

6.9.9 Black Boxing135

6.10 Managing Multiple Clock Domains135

6.11 Managing Late Changes to the Netlist136

6.10.3 Set False Paths Across Known Asynchronous Boundaries136

6.10.2 Identify Synchronizing Flip-Flops with Unique Names136

6.10.1 Isolate the Asynchronous Interfaces136

6.11.1 Complete Resynthesis137

6.11.2 Partial Resynthesis137

6.11.3 Editing the Gate-Level Netlist137

6.12 Summary138

Chapter 7 Quality Framework139

7.1 Introduction139

7.2 The Directory Structure139

7.2.1 engineer_work_area140

7.2.2 reference_files141

7.2.3 top_level_simulations141

7.2.4 release_area141

7.2.5 Source Control142

7.2.6 Synthesis Directory142

7.2.7 Templates142

7.3 Documentation Storage143

7.4 Freezing Documents and Controlled Updates143

7.5 Fault Report Database143

7.8 Company-Defined Procedures144

7.7 Makefiles/Simulation Scripts144

7.6 Source Code Control144

7.9 Summary145

Chapter 8 Planning and Tracking ASIC Projects147

8.1 Overview147

8.2 Basic Planning Concepts147

8.3 Process for Creating a Plan150

8.3.1 Definition of Deliverables151

8.3.2 Task Breakdown152

8.3.3 Assigning Dependencies153

8.3.4 Allocation of Resources154

8.3.5 Refining the Plan155

8.3.6 Reviewing the Plan156

8.4 Tracking157

8.4.1 Tracking Methods158

8.5 Summary159

Chapter 9 Reducing Project Risks161

9.1 Introduction161

9.2 Trade-Offs Between Functionality,Performance,Cost and Timescales162

9.3 Minimizing Development Risks163

9.3.2 ASIC Architecture164

9.3.1 Selecting the Team164

9.3.3 High-Level Architectural Modeling165

9.3.4 Interface Specifications165

9.3.5 Managing Changing Design Requirements166

9.3.6 Programmability166

9.3.7 Regular Design Reviews167

9.3.8 Early Trial Synthesis168

9.3.9 Early Trial Layouts168

9.4 Reducing the Risk of Design Bugs168

9.4.1 Simulation169

9.4.2 Emulation170

9.4.3 FPGAs170

9.4.4 Fast-Turnaround ASICs171

9.4.5 Early Sign-Off172

9.5 Risks in Meeting ASIC Vendor Criteria173

9.5.1 Power Consumption Issues173

9.5.2 Package/Pin-Out174

9.6 Summary174

10.2 Using the Vendor's Expertise177

Chapter 10 Dealing with the ASIC Vendor177

10.1 Introduction177

10.3 Vendor Selection178

10.3.1 RFQ Details179

10.3.2 Vendor Comparisons182

10.4 ASIC Vendor Services183

10.5 Effect of the Vendor on Timescales184

10.5.1 Layout184

10.5.3 Production Chips186

10.5.4 Liaison with the Vendor During the Project186

10.5.2 Provision of Engineering Samples186

10.6 Summary188

Chapter 11 Motivation and People Management189

11.1 Introduction189

11.2 Managing Engineers with Different Experience Levels189

11.3 Maslow's Hierarchy of Needs191

11.3.1 Physiological Needs and Safety Needs191

11.3.2 Social Contact191

11.3.3 Self-Esteem192

11.4.1 Different Personalities193

11.3.4 Self-Actualization193

11.4 Getting to Know the Team193

11.4.2 Interacting with the Impulsive Type194

11.4.3 Interacting with the Reflective Type195

11.5 Goal Setting195

11.6 Communicating Project Information196

11.6.1 Project Meetings196

11.6.3 Competitors'Products197

11.6.4 Highlighting the Importance of the Project to the Business197

11.6.2 Marketing Information197

11.6.5 Show Enthusiasm and Have Fun198

11.7 Training198

11.7.1 Technical Training198

11.7.2 Personal Training199

11.7.3 Product/Design-Specific Training199

11.8 Summary199

Chapter 12 The Team201

12.1 Introduction201

12.2.2 People-and Team-Management Skills202

12.2 The Project Leader/Project Manager202

12.2.1 Technical Skills202

12.3 The Wider Team203

12.4 Key Roles Within the Team204

12.4.1 System Architect204

12.4.2 Tools Expert205

12.4.3 Testbench Engineers205

12.4.4 Team Leaders206

12.5 Summary207

13.2 Running Meetings209

Chapter 13 Project Manager Skills209

13.1 Introduction209

13.3 Interviewing210

13.4 Time Management212

13.5 Summary213

Chapter 14 Design Tools215

14.1 Introduction215

14.3.2 High-Level Entry Tools216

14.3.1 Text Editors216

14.3 Input Tools216

14.2 Hierarchy Tools216

14.4 Code Analysis Tools217

14.5 Revision Management Tools217

14.6 Testbench and Validation Tools217

14.6.1 Testbench Tools218

14.6.2 Code Coverage218

14.6.3 Standard Simulators218

14.6.5 Hardware Accelerators219

14.6.4 Cycle-Based Simulators219

14.6.6 Emulation220

14.6.7 Cosimulation220

14.6.8 Formal Verification220

14.7 Synthesis Tools221

14.8 Static-Timing Analyzers222

14.9 Summary222

Bibliography223

About the Authors225

Index227