现代VLSI设计 片上系统设计 第3版 改编版2025|PDF|Epub|mobi|kindle电子书版本百度云盘下载

现代VLSI设计 片上系统设计 第3版 改编版PDF格式电子书版下载

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1 Digital Systems and VLSI1

1.1 Why Design Integrated Circuits?1

1.2 Integrated Circuit Manufacturing4

1.2.1 Technology4

1.2.2 Economics6

1.3 CMOS Technology15

1.3.1 CMOS Circuit Techniques15

1.3.2 Power Consumption16

1.3.3 DesignandTestability17

1.4 Integrated Circuit Design Techniques18

1.4.1 Hierarchical Design19

1.4.2 Design Abstraction22

1.4.3 Computer-Aided Design28

1.5 ALook into the Future30

1.6 Summary31

1.7 References31

1.8 Problems32

2 Transistors and Layout33

2.1 Introduction33

2.2 Fabrication Processes34

2.2.1 Overview34

2.2.2 Fabrication Steps37

2.3 Transistors40

2.3.1 Structure of the Transistor40

2.3.2 A Simple Transistor Model45

2.3.3 Transistor Parasitics48

2.3.4 Tub Ties and Latchup50

2.3.5 Advanced Transistor Characteristics53

2.3.6 Leakage and Subthreshold Currents60

2.3.7 Advanced Transistor Structures61

2.3.8 Spice Models61

2.4 Wires and Vias62

2.4.1 Wire Parasitics65

2.4.2 Skin Effect in Copper Interconnect72

2.5 Design Rules74

2.5.1 Fabrication Errors75

2.5.2 Scalable Design Rules77

2.5.3 SCMOS Design Rules79

2.5.4 Typical Process Parameters83

2.6 Layout Design and Tools83

2.6.1 Layouts for Circuits83

2.6.2 Stick Diagrams88

2.6.3 Layout Design and Analysis Tools90

2.6.4 Automatic Layout94

2.7 References97

2.8 Problems97

3 Logic Gates105

3.1 Introduction105

3.2 Static Complementary Gates106

3.2.1 Gate Structures106

3.2.2 Basic Gate Layouts110

3.2.3 Logic Levels113

3.2.4 Delay and Transition Time118

3.2.5 Power Consumption127

3.2.6 The Speed-Power Product130

3.2.7 Layout and Parasitics131

3.2.8 Driving Large Loads134

3.3 Switch Logic135

3.4 Alternative Gate Circuits136

3.4.1 Pseudo-nMOS Logic137

3.4.2 DCVS Logic139

3.4.3 Domino Logic141

3.5 Low-Power Gates146

3.6 Delay Through Resistive Interconnect152

3.6.1 Delay Through an RC Transmission Line152

3.6.2 Delay Through RC Trees155

3.6.3 Buffer Insertion in RC Transmission Lines159

3.6.4 Crosstalk Between RC Wires161

3.7 Delay Through Inductive Interconnect164

3.7.1 RLC Basics165

3.7.2 RLC Transmission Line Delay166

3.7.3 Buffer Insertion in RLC Transmission Lines167

3.8 References169

3.9 Problems171

4 Combinational Logic Networks177

4.1 Introduction177

4.2 Standard Cell-Based Layout178

4.2.1 Single-Row Layout Design179

4.2.2 Standard Cell Layout Design188

4.3 Simulation190

4.4 Combinational Network Delay194

4.4.1 Fanout195

4.4.2 Path Delay196

4.4.3 Transistor Sizing201

4.4.4 Automated Logic Optimization210

4.5 Logic and Interconnect Design211

4.5.1 Delay Modeling212

4.5.2 Wire Sizing213

4.5.3 Buffer Insertion214

4.5.4 Crosstalk Minimization216

4.6 Power Optimization221

4.6.1 Power Analysis221

4.7 Switch Logic Networks225

4.8 Combinational Logic Testing229

4.8.1 Gate Testing231

4.8.2 Combinational Network Testing234

4.9 References236

4.10 Problems236

5 Sequential Machines241

5.1 Introduction241

5.2 Latches and Flip-Flops242

5.2.1 Categories of Memory Elements242

5.2.2 Latches244

5.2.3 Flip-Flops251

5.3 Sequential Systems and Clocking Disciplines252

5.3.1 One-Phase Systems for Flip-Flops255

5.3.2 Two-Phase Systems for Latches257

5.3.3 Advanced Clocking Analysis265

5.3.4 Clock Generation272

5.4 Sequential System Design273

5.4.1 Structural Specification of Sequential Machines273

5.4.2 State Transition Graphs and Tables275

5.4.3 State Assignment284

5.5 Power Optimization290

5.6 Design Validation291

5.7 Sequential Testing293

5.8 References300

5.9 Problems300

6 Subsystem Design303

6.1 Introduction303

6.2 Subsystem Design Principles306

6.2.1 Pipelining306

6.2.2 Data Paths308

6.3 Combinational Shifters311

6.4 Adders314

6.5 ALUs321

6.6 Multipliers322

6.7 High-Density Memory331

6.7.1 ROM333

6.7.2 Static RAM335

6.7.3 The Three-Transistor Dynamic RAM339

6.7.4 The One-Transistor Dynamic RAM340

6.8 References344

6.9 Problems344

7 Floorplanning347

7.1 Introduction347

7.2 Floorplanning Methods348

7.2.1 Block Placement and Channel Definition352

7.2.2 Global Routing358

7.2.3 Switchbox Routing360

7.2.4 Power Distribution361

7.2.5 Clock Distribution364

7.2.6 Floorplanning Tips369

7.2.7 Design Validation370

7.3 Off-Chip Connections371

7.3.1 Packages371

7.3.2 The I/O Architecture375

7.3.3 Pad Design376

7.4 References379

7.5 Problems381

8 Architecture Design387

8.1 Introduction387

8.2 Hardware Description Languages388

8.2.1 Modeling with Hardware Description Languages388

8.2.2 VHDL393

8.2.3 Verilog402

8.2.4 C as a Hardware Description Language409

8.3 Register-Transfer Design410

8.3.1 Data Path-Controller Architectures412

8.3.2 ASM ChartDesign413

8.4 High-Level Synthesis422

8.4.1 Functional Modeling Programs424

8.4.2 Data425

8.4.3 Control435

8.4.4 Dataand Control441

8.4.5 Design Methodology443

8.5 Architectures for Low Power444

8.5.1 Architecture-Driven Voltage Scaling445

8.5.2 Power-Down Modes446

8.6 Systems-on-Chips and Embedded CPUs447

8.7 Architecture Testing453

8.8 References457

8.9 Problems457

9 Chip Design461

9.1 Introduction461

9.2 Design Methodologies461

9.3 Kitchen Timer Chip470

9.3.1 Timer Specification and Architecture471

9.3.2 Architecture Design473

9.3.3 Logic and Layout Design478

9.3.4 Design Validation485

9.4 Microprocessor Data Path488

9.4.1 Data Path Organization489

9.4.2 Clocking and Bus Design490

9.4.3 Logic and Layout Design492

9.5 References494

9.6 Problems495

10 CAD Systems and Algorithms497

10.1 Introduction498

10.2 CAD Systems498

10.3 Switch-Level Simulation499

10.4 Layout Synthesis501

10.4.1 Placement503

10.4.2 Global Routing506

10.4.3 Detailed Routing508

10.5 Layout Analysis510

10.6 Tuning Analysis and Optimization512

10.7 Logic Synthesis517

10.7.1 Technology-Independent Logic Optimization518

10.7.2 Technology-Dependent Logic Optimizations525

10.8 Test Generation528

10.9 Sequential Machine Optimizations530

10.10 Scheduling and Binding532

10.11 Hardware/Software Co-Design534

10.12 References535

10.13 Problems535

A Chip Designer's Lexicon539

B Chip Design Projects557

B.1 Class Project Ideas557

B.2 Project Proposal and Specification558

B.3 Design Plan559

B.4 Design Checkpoints and Documentation562

B.4.1 Subsystems Check563

B.4.2 First Layout Check563

B.4.3 Project Completion563

C Kitchen Timer Model565

C.1 Hardware Modeling in C565

C.1.1 Simulator567

C.1.2 Sample Execution573

References577

Index593