现代VLSI电路设计 英文版2025|PDF|Epub|mobi|kindle电子书版本百度云盘下载

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1 Digital Systems and VLSI1

1．1 Why Design Integrated Circuits?1

1．2 Integrated Circuit Manufacturing3

1．2．1 Technology3

1．2．2 Economics6

1．3 CMOS Technology15

1．3．1 CMOS Circuit Techniques15

1．3．2 Power Consumption16

1．3．3 Design and Testability17

1．4 Integrated Circuit Design Techniques18

1．4．1 Hierarchical Design19

1．4．2 Design Abstraction22

1．4．3 Computer-Aided Design28

1．5 A Look into the Future30

1．6 Summary31

1．7 References31

1．8 Problems32

2 Transistors and Layout33

2．1 Introduction33

2．2 Fabrication Processes34

2．2．1 Overview34

2．2．2 Fabrication Steps36

2．3 Transistors39

2．3．1 Structure of the Transistor39

2．3．2 A Simple Transistor Model44

2．3．3 Transistor Parasitics47

2．3．4 Tub Ties and Latchup48

2．3．5 Advanced Transistor Characteristics52

2．3．6 Advanced Transistor Structures60

2．3．7 Spice Models61

2．4 Wires and Vias63

2．4．1 Wire Parasitics65

2．5 Design Rules71

2．5．1 Fabrication Erros72

2．5．2 Scalable Design Rules74

2．5．3 SCMOS Design Rules75

2．5．4 Typical Process Parameters79

2．6．1 Layouts for Circuits81

2．6 Layout Design and Tools81

2．6．2 Stick Diagrams84

2．6．3 Hierarchical Stick Diagrams86

2．6．4 Layout Design and Analysis Tools91

2．6．5 Automatic Layout95

2．7 References98

2．8 Problems99

3 Logic Gates107

3．1 Introduction107

3．2 Combinational Logic Functions107

3．3 Static Complementary Gates110

3．3．1 Gate Structures110

3．3．2 Basic Gate Layout115

3．3．3 Logic Levels119

3．3．4 Delay121

3．3．5 Power Consumption129

3．3．6 The Speed-Power Product133

3．3．7 Layout and Parasitics133

3．3．8 Driving Large Loads137

3．4． Wires and Delay138

3．4．1 Elmore Delay Model138

3．4．2 Wire Sizing139

3．4．3 RC Trees141

3．5 Switch Logic143

3．6 Alternative Gate Circuits145

3．6．1 Pseudo-nMOS Logic146

3．6．2 DCVS Logic149

3．6．3 Domino Logic150

3．7 References155

3．8 Problems156

4 Combinational Logic Networks161

4．1 Introduction161

4．2 Layout Design Methods161

4．2．1 Single-Row Layout Design162

4．2．2 Standard Cell Layout Design171

4．3 Simulation174

4．4 Combinational Network Delay177

4．4．1 Fanout178

4．4．2 Path Delay180

4．4．3 Transistor Sizing184

4．4．4 Automated Logic Optimization188

4．5 Crosstalk189

4．6 Power Optimization195

4．7 Switch Logic Networks199

4．8 Combinational Logic Testing203

4．8．1 Gate Testing205

4．8．2 Combinational Networks Testing208

4．9 References210

4．10 Problems210

5 Sequential Machines215

5．1 Introduction215

5．2 Latches and Flip-Flops215

5．2．1 Categories of Memory Elements215

5．2．2 Latches217

5．2．3 Flip-Flops224

5．3 Sequential Systems and Clocking Disciplines226

5．3．1 One-Phase Systems for Flip-Flops229

5．3．2 Two-Phase Systems for Latches229

5．3．3 Advanced Clocking Analysis239

5．3．4 Clock Generation246

5．4 Sequential System Design247

5．4．1 Structural Specification of Sequential Machines247

5．4．2 State Transition Graphs and Tables249

5．4．3 State Assignment258

5．5 Power Optimization264

5．6 Design Validation265

5．7 Sequential Testing267

5．8 References274

5．9 Problems275

6 Subsystem Design277

6．1 Introduction277

6．2 Subsystem Design Principles279

6．2．1 Pipelinig279

6．2．2 Data Paths281

6．3 Combinational Shifters285

6．4 Adders287

6．5 ALUs296

6．6 Multipliers297

6．7 High、Density Memory306

6．7．1 ROM308

6．7．2 Static RAM309

6．7．3 The Three-Transistor Dynamic RAM313

6．7．4 The One-Transistor Dynamic RAM314

6．8 Field-Programmable Gate Arrays318

6．9 Programmable Logic Arrays318

6．10 References322

6．11 Problems323

7 Floorplanning325

7．1 Introduction325

7．2 Floorplanning Methods325

7．2．1 Block Placement and Channel Definition329

7．2．2 Global Routing334

7．2．3 Switchbox Routing336

7．2．4 Power Distribution337

7．2．5 Clock Distribution340

7．2．6 Floorplanning Tips345

7．2．7 Design Validation346

7．3 Off-Chip Connections347

7．3．1 Packages347

7．3．2 The I/O Architecture351

7．3．3 Pad Design352

7．4 References356

7．5 Problems357

8 Architecture Design363

8．1 Introduction363

8．2 Register-Transfer Design364

8．2．1 Register-Transfer Simulation Programs365

8．2．2 Data Path-Controller Architectures367

8．2．3 ASM Chart Design368

8．3 High-Level Synthesis377

8．3．1 Functional Modeling Programs379

8．3．2 Data380

8．3．3 Control390

8．3．4 Data and Control397

8．3．5 Design Methodology399

8．4 Architectures for Low Power400

8．4．1 Architecture-Driven Voltage Scaling400

8．4．2 Power-Down Modes402

8．5 Architecture Testing403

8．7 Problems407

8．6 References407

9 Chip Design411

9．1 Introduction411

9．2 Design Methodologies411

9．3 Kitchen Timer Chip419

9．3．1 Timer Specification and Architecture420

9．3．2 Architecture Design422

9．3．3 Logic and Layout Design427

9．3．4 Design Validation435

9．4 PDP-8 Data Path437

9．4．1 PDP-8 Instruction Set438

9．4．2 Register-Transfer Design442

9．4．3 Clocking and Bus Desing444

9．4．4 Logic and Layout Design447

9．5 References451

9．6 Problems452

10 CAD Systems and Algorithms453

10．1 Introduction453

10．2 CAD Systems454

10．3 Simulation455

10．3．1 Event-Driven Simulation455

10．3．2 Switch Simulation457

10．4 Layout Synthesis459

10．4．1 Placement460

10．4．2 Global Routing463

10．4．3 Detailed Routing465

10．5 Layout Analysis468

10．6 Timing Analysis and Optimization470

10．7 Logic Synthesis474

10．7．1 Technology-Independent Logic Optimization476

10．7．2 Technology-Dependent Logic Optimizations483

10．8 Test Generation486

10．9 Sequential Machine Optimizations488

10．10 Scheduling and Binding490

10．11 Hardware/Software Co-Design492

10．12 References493

10．13 Problems493

Appendix A: A Chip Designer s Lexicon499

Appendix B: Chip Design Projects511

B.1 Class Project Ideas511

B.2 Project Proposal and Specification513

B.3 Design Plan514

B.4 Design Checkpoints and Documentation517

B.4.1 Subsystems Check517

B.4.2 First Layout Check517

B.4.3 Project Completion517

Appendix C: Design Modeling519

C．1Introduction519

C．2 Hardware Modeling in VHDL519

C．3 Hardware Modeling in C525

C．3．1 Simulator528

C．3．2 Sample Execution533

References537

Index551